Be sure you have read all assigned sections of chapter 4.
Do the following problems. You may write out your answers by hand or using a word processor or other program, but please submit hard copy, either in class or in my mailbox in the department office.
(a) and rt, rs1, rs2
(b) sw rt, offset(rs)
Problem 4.1 wants you to give values for the following signals: RegWrite, MemRead, ALUMux, MemWrite, ALUop (can be the name of the operation, e.g., AND), RegMux, Branch.
In problems 4.1.2 and 4.1.3, ``resources'' means the labeled blocks in Figure 4.2 -- Instruction Memory, Registers, etc.
(a) sw $4, -100($16)
(b) slt $1, $2, $3
(Modification: This question is sufficiently beyond the scope of what we did in class that I'm making it extra-credit only.)
Section 4.4 of the textbook discusses how information flows through the datapath of Figure 4.17 for three instructions (R-format, lw, and beq -- this is the discussion illustrated by Figures 4.19 through 4.24)). There is also a discussion of what must be added to support the j instruction, culminating in Figure 4.24.
For each of the specified instructions (jr and jal), first describe (as a numbered list of steps) what execution of the instruction needs to involve and what changes (if any) you would need to make to the design shown in Figure 4.24 to make it work. (If you need to make changes to the figure, it might be clearest to print/photocopy the figure and mark it up.)
(Modification: This question is sufficiently beyond the scope of what we did in class that I'm making it extra-credit only.)
Section 4.9 of the textbook discusses changes to the pipelined implementation needed to support exceptions. Describe how you could adapt this approach to the single-cycle implementation -- that is, describe what changes you would need to make to the design shown in Figure 4.24. (If you need to make changes to the figure, it might be clearest to print/photocopy the figure and mark it up.)