(Material [in brackets] is optional.)

[
add $t0, $t1, $t2  at addr 0x4
with PC = 0x4, $t1 = 5, and $t2 = 2

instruction 0x012a4020

opcode 000000
rs 01001 
rt 01010
rd 01000
fcn field 100000 (0x20)
(other fields unused)
]

PC:
	input 0x8
	output 0x4

Instruction memory:
	input 0x4
	output instruction 0x012a4020

Inputs and output of top-left adder:
	in1 0x4 (PC)
	in2 4
	out 0x8

Inputs and output of top-right adder:
	in1 not used
	in2 not used
	output not used

Control signals:
	RegDst	1
	ALUSrc	0
	MemtoReg 0
	RegWrite 1
	MemRead	0	
	MemWrite 0
	Branch 0
	ALUOp 10

Inputs and output of register file:
	Read register 1 9 ($t1)
	Read register 2 10 ($t2)
	Write register 8 ($t0)
	Write data 0x6 7 (from ALU)
	Read data 1 5 (from $t1)
	Read data 2 2 (from $t2)

Inputs and output of the main ALU, including the control signals:
	ALU control 0010 (add)
	ALU input 1 5 (from reg)
	ALU input 2 2 (from reg)
	ALU result 7
	Zero not used

Inputs and output of data memory:
	Address not used
	Write signal 0
	Write not used
	Read signal 0
	Read not used

State elements to be changed:
	PC (to 0x8)
	register file $t0 to 7
	data memory not changed