(Material [in brackets] is optional.)

[
beq $t1, $t2, LBL
with PC = 0x4, $t1 = 10, $t2 = 10, LBL translating to an offset of 3

instruction 0x112a0003

0001 0001 0010 1010 0000 0000 0000 0003
000100 01001 01010 0000000000000003

opcode 000100
rs 01001 (9)
rt 01010 (10)
imm 0x3
]

PC:
	input 0x14 (branch target)
	output 0x4

Instruction memory:
	input 0x4
	output 0x112a0003

Inputs and output of top-left adder:
	in1 0x4 
	in2 4
	out 0x8 

Inputs and output of top-right adder:
	in1 0x8
	in2 3 * 4, i.e, 12 (0xc)
	output 0x14

Control signals:
	RegDst	X
	ALUSrc	0
	MemtoReg X
	RegWrite 0
	MemRead	0
	MemWrite 0
	Branch 1
	ALUOp 01

Inputs and output of register file:
	Read register 1 9 ($t1)
	Read register 2 10 ($t2)
	Write register unused
	Write data 0x6 unused
	Read data 1 10 ($t1)
	Read data 2 10 ($t2)

Inputs and output of the main ALU, including the control signals:
	ALU control 0110 (subtract)
	ALU input 1 10 ($t1)
	ALU input 2 10 ($t2)
	ALU result 0
	Zero 1

Inputs and output of data memory:
	Address not used
	Write signal 0
	Write not used
	Read signal 0
	Read not used

State elements to be changed:
	PC 0x14 (branch target)
	register file no changes
	data memory no changes